Recently, software or hardware may execute a designated task. Generally, software tends to consume more power in executing a task compared to hardware executing the same task. On the other hand, if the hardware is used to execute the task, though power consumption may be reduced, unlike software, hardware offers no flexibility, and dedicated hardware must be prepared. Therefore, to enjoy the advantage of executing the task using hardware without preparing any dedicated hardware, a highly-flexible dynamically reconfigurable circuit that can cope with a task when the circuit executes the task, is attracting more attention.
FIG. 26 is a diagram of a hardware rewriting process of a conventional dynamically reconfigurable circuit. As depicted in FIG. 26, to rewrite hardware in a dynamically reconfigurable circuit 2600-1, the entire logic 2601 (in this example, an encryption algorithm “advanced encryption standards” (AES)) having therein plural processor elements (PE)s to be rewritten, is mapped at one time. Thereafter, a necessary number of PEs to execute the logic 2601 of the PEs prepared in the dynamically reconfigurable circuit 2600-1 are rewritten and, thereby, the circuit 2600-1 is reconfigured dynamically into a dynamically reconfigurable circuit 2600-2 for executing the AES.
A long rewriting process time and high power consumption are required to rewrite, at one time, all the PEs that realize the logic 2601 as the dynamically reconfigurable circuit 2600-2 of FIG. 26. With the above time and power consumption, the advantage obtained in executing the task using the hardware, that is, a low power consumption is lost. A solution of executing partial rewriting has also been provided.
FIG. 27 is a diagram of a hardware rewriting process in plural dynamically reconfigurable circuits. In the example depicted in FIG. 27, dynamically reconfigurable circuits 2700-1 to 2700-4 sequentially execute tasks. For example, while the dynamically reconfigurable circuit 2700-1 is executing logic 2701 that realizes an encryption algorithm AES, rewriting processes of PEs are being executed in the other dynamically reconfigurable circuits 2700-2 to 2700-4 in the background to form logic that copes with tasks to be executed next and thereafter.
More specifically, mapping of logic 2702 that realizes an encryption algorithm “Camellia” is executed in the dynamically reconfigurable circuit 2700-2. Similarly, mapping of logic 2703 that realizes an encryption algorithm “TDEA” and mapping of logic 2704 that realizes an encryption algorithm “MISTY1” are respectively executed in the dynamically reconfigurable circuits 2700-3 and 2700-4. In this manner, a standby state due to the above rewriting processes may be suppressed by executing in parallel the rewriting processes of the dynamically reconfigurable circuits. Therefore, the rewriting process time that conventionally is the standby time for a user may be concealed superficially.
As described, a partial rewriting process is also effective for suppressing the rewriting process time period and the power consumed by the rewriting process. More specifically, logic to be rewritten (for example, the logic 2601 of FIG. 26) is divided and partially mapped. At this time, the order in which the rewriting processes are executed is statically fixed because the division of the logic is executed at the compiler level. To divide the logic at the compiler level as above, scheduling information concerning the tasks to be executed by each dynamically reconfigurable circuit needs to be obtained in advance. When the scheduling information is obtained in advance and the tasks are executed according to the schedule, the rewriting process is partially realized and consequently, the rewriting time period and the power consumption that are needed once are suppressed.
Refer to Japanese Laid-Open Patent Publication No. 2003-223476 and Japanese Laid-Open Patent Publication No. 2006-163815 as examples.
However, even when the above countermeasure is taken, high power consumption is still needed for the rewriting process of a PE associated with the reconfiguration of the dynamically reconfigurable circuit. Because the power consumption for executing the rewriting process is significantly high compared to that of an ordinary process, the load on the power supply is also high. Therefore, a problem has arisen in that, in a portable apparatus for which battery-operation is assumed, reconfiguration processing cannot be actively used even when a dynamically reconfigurable circuit is implemented on such an apparatus.
Even when a rewriting process of plural dynamically reconfigurable circuits is executed in the background as described, the effect of concealing the rewriting process time period is actually achieved. However, the problem of high power consumption remains because the rewriting process is executed for the dynamically reconfigurable circuits concurrently. Further, it has been experimentally demonstrated that the power consumption for reconfiguration processing becomes higher when more resources (in this case, the reconfigurable circuits) are used (see, e.g., Nishimura, Takashi, et al, “Power analysis on Dynamic Reconfigurable Processor”, IEICE Tech. Rep., RECONF 2007-41 (2007-11), pp. 31-36).
FIG. 28 is a graph of power consumption for the hardware rewriting process. A graph 2800 depicts the variation of the power consumption when the rewriting process of the dynamically reconfigurable circuits 2700-2 to 2700-4 is executed in the background while the tasks are being executed in the dynamically reconfigurable circuit 2700-1 as described with reference to FIG. 27. On a curve 2801, the execution of the tasks in the dynamically reconfigurable circuit 2700-1 and the rewriting process in the dynamically reconfigurable circuits 2700-2 to 2700-4 concentrate at a time T1 and, therefore, high power is needed simultaneously. Therefore, a problem has arisen in that a significant voltage drop of the battery that drives the entire system occurs due to the power consumption by the operations at the time T1.
Even when the rewriting process is partially executed as described, the logic must be divided at the compiler level and processing to acquire data concerning power is necessary in advance. Therefore, a problem has arisen in that the partial rewriting process is applicable only to limited types of applications such as reproduction of stream data.
FIG. 29 is a graph of variations in power consumption for the partial rewriting process of hardware. In a graph 2900 of FIG. 29, a curve 2901 represents variations in the peak of power consumption estimated in advance. A curve 2902 represents variations in the peak of actual power consumption. Even in a case where variations in the peak of the power consumption is estimated in advance, when the process is actually executed, the power load varies due to the utilization environment and external factors (such as the power for processes in other phases) and the actual variation of the peak, the curve 2902, often significantly deviates from the estimated variation of the peak. When the peak power, the curve 2902, becomes higher than estimated, a gap occurs between the actual power and the power calculated at the scheduling and the fluctuation of the power displayed becomes significant. Consequently, the load on the battery becomes significant and a problem arises in that the life of the battery is reduced.